hw.dri

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Property Value
OID 6.7fffd21d
Description DRI args
Label
Type node
Format N
Flags
  • RD, Can read the value
  • WR, Can write the value
  • RW, RD and WR


Children:
Child Description
hw.dri.timestamp_precision
hw.dri.vblank_offdelay
hw.dri.0
hw.dri.edid_firmware Do not probe monitor, use specified EDID blob from built-in data or /lib/firmware instead.
hw.dri.drm_fbdev_overalloc Overallocation of the fbdev buffer (%) [default=100]
hw.dri.fbdev_emulation Enable legacy fbdev emulation [default=true]
hw.dri.timestamp_precision_usec Max. error on timestamps [usecs]
hw.dri.vblankoffdelay Delay until vblank irq auto-disable [msecs] (0: never disable, <0: disable immediately)
hw.dri.poll help drm kms poll
hw.dri.always_interruptible always allow a thread to be interrupted in driver wait
hw.dri.error_panic panic if an ERROR is hit
hw.dri.drm_debug_persist keep drm debug flags post-load
hw.dri.skip_ddb go straight to dumping core
hw.dri.drm_debug drm debug flags
hw.dri.edid_fixup Minimum number of valid EDID header bytes (0-8, default 6)
hw.dri.debug Enable debug output, where each bit enables a debug category. Bit 0 (0x01) will enable CORE messages (drm core code) Bit 1 (0x02) will enable DRIVER messages (drm controller code) Bit 2 (0x04) will enable KMS messages (modesetting code) Bit 3 (0x08) will enable PRIME messages (prime code) Bit 4 (0x10) will enable ATOMIC messages (atomic code) Bit 5 (0x20) will enable VBL messages (vblank code) Bit 7 (0x80) will enable LEASE messages (leasing code) Bit 8 (0x100) will enable DP messages (displayport code)
hw.dri.dp_aux_i2c_transfer_size Number of bytes to transfer in a single I2C over DP AUX CH message, (1-16, default 16)
hw.dri.dp_aux_i2c_speed_khz Assumed speed of the i2c bus in kHz, (1-400, default 10)